Effects of Logic Glitch and (Area-Power dissipation) leakage on Cryptosystems Using Clock Gating Technique to Enhance web Etiquette.

Abstract

Abstract

Technological developments have taken place over the past century to improve communication systems and make life easier for ordinary people. The explosion of devices and services has made communication systems faster and more reliable. However, these upgrades come at a price. Power consumption is one of the most concerning cost factors. In recent years, the solution has been to have a larger, more powerful battery, as long as it does not restrict mobility. Today's economic and environmental problems compel us to consider alternative solutions, like methods for lowering the power consumption of digital devices. This study focuses on using digital circuits, which promise to deliver good energy efficiency and desirable performance at very low voltage savings. Certain digital switches are allegedly redundant and not required for the circuit to function properly, yet they continue to use energy. So, one of the primary issues for low power design is reducing such redundant switches. Subthreshold conduction in digital circuits is typically seen as  parasitic leakag. Sub-threshold activities thereby reduce the problem of lowering power consumption, but do so at the expense of system throughput deterioration, fluctuations in system stability and functionality, temperature variations, and most critically, design space utilization. In order to minimize some of these redundant switches and to make circuits more energy-efficient while maintaining functionality. This study suggests two novel techniques. It uses an optimization method based on threshold voltage to reduce glitch power. A glitch-free circuit  is created using an algorithm, while still maintaining the requisite delay performance.